Hexagonal TSV Bundle Topology for 3-D ICs
نویسندگان
چکیده
منابع مشابه
Challenges and Emerging Solutions in Testing TSV-Based 21⁄2 D-and 3D-Stacked ICs
Through-Silicon Vias (TSVs) provide high-density, low-latency, and low-power vertical interconnects through a thinned-down wafer substrate, thereby enabling the creation of 2.5Dand 3D-Stacked ICs. In 2.5D-SICs, multiple dies are stacked side-by-side on top of a passive silicon interposer base containing TSVs. 3D-SICs are towers of vertically stacked active dies, in which the vertical inter-die ...
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Interconnect delays are increasingly dominating IC performance due to increases in chip size and reduction in the minimum feature size [1]. In spite of new materials like Cu and a low-k dielectric interconnect delay is expected to be substantial below 130 nm technology node, thereby severely limiting chip performance [2]. Therefore, the need exists for alternative technologies to overcome this ...
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ژورنال
عنوان ژورنال: IEEE Transactions on Circuits and Systems II: Express Briefs
سال: 2017
ISSN: 1549-7747,1558-3791
DOI: 10.1109/tcsii.2016.2551552